25LC010A データシートの表示（PDF） - Microchip Technology
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25LC010A Datasheet PDF : 24 Pages
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25LCXXXA
3.2 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25LCXXXA fol-
lowed by the 8-bit address. For the 25LC040A the MSb
(A8) is sent to the slave during the instruction
sequence. See Figure 3-1 for more details. After the
correct READ instruction and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO pin. The data stored in the memory at the
next address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address 000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 3-1).
3.3 Write Sequence
Prior to any attempt to write data to the 25LCXXXA, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25LCXXXA. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruc-
tion, followed by the 8-bit address, and then the data to
be written. Up to 16 bytes can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. Addi-
FIGURE 3-1:
READ SEQUENCE
tionally a page address begins with ‘XXXX 0000’ and
ends with ‘XXXX 1111’. If the internal address counter
reaches ‘XXXX 1111’ and clock signals continue to be
applied to the ship, the address counter will roll back to
the first address of the page and over-write any data
that previously existed in those locations.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a page
write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-6 and Figure 3-4
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction+Address MSb
Lower Address Byte
0 0 0 0 A8 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0
High-impedance
Data Out
76543210
For the 24LC010A device both A8 and A7 are don’t cares.
For the 24LC020A device A8 is a don’t care.
© 2009 Microchip Technology Inc.
Preliminary
DS22136B-page 9
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