28F128L30 データシートの表示（PDF） - Intel
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28F128L30 Datasheet PDF : 100 Pages
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28F640L30, 28F128L30, 28F256L30
2.4.1
Signal Descriptions for 128/0 and 256/0 Stacked-CSP
Table 2 describes the active signals used on the 128/0 and 256/0-Mbit S-CSP.
Table 2. Device Signal Descriptions for S-CSP (Sheet 1 of 2)
Symbol
A[Max:0]
D[15:0]
CE#1
CE#2
S-CS1#
S-CS2
P-CS#
OE#1
OE#2
R-OE#
WE#
R-WE#
CLK
WAIT
Type
Input
Input/
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Description
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 128-Mbit Die: A[Max] = A22
• 256-Mbit Die: A[Max] = A23
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs
data during read cycles. Data signals float when the device or its outputs are
deselected. Data is internally latched during writes.
FLASH CHIP ENABLE: Low-true: CE#-low selects the associated flash memory
die. When asserted, flash internal control logic, input buffers, decoders, and sense
amplifiers are active. When deasserted, the associated flash die is deselected,
power is reduced to standby levels, data and WAIT outputs are placed in high-Z
state.
CE#1 selects flash die #1; CE#2 selects flash die #2. CE#2 is available on stacked
combinations with two flash die and is RFU (Reserved For Future Use) on stacked
combinations with only one flash die.
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal
control logic, input buffers, decoders, and sense amplifiers are active. When either/
both SRAM chip selects are deasserted (S-CS1# = VIH or S-CS2 = VIL), the SRAM
is deselected and its power is reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
PSRAM CHIP SELECT: Low-true; When asserted, PSRAM internal control logic,
input buffers, decoders, and sense amplifiers are active. When deasserted, the
PSRAM is deselected and its power is reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers.
OE#-high disables the flash output buffers, and places the flash outputs in High-Z.
OE#1 controls the outputs of flash die #1; OE#2 controls the outputs of flash die #2.
OE#2 is available on stacked combinations with two flash die and is RFU on stacked
combinations with only one flash die.
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output
buffers. R-OE#-high disables the RAM output buffers, and places the selected RAM
outputs in High-Z.
Treat this signal as NC (No Connect) for this device.
FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die.
Address and data are latched on the rising edge of WE#.
RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die.
Treat this signal as NC (No Connect) for this device.
FLASH CLOCK: Synchronizes the device with the system’s bus frequency in
synchronous-read mode and increments the internal address generator. During
synchronous read operations, addresses are latched on the rising edge of ADV#, or
on the next valid CLK edge with ADV# low, whichever occurs first.
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads.
Configuration Register bit 10 (CR.10, WT) determines its polarity when asserted.
With CE# and OE# at VIL, WAIT’s active output is VOL or VOH when CE# and OE#
are asserted. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data
when asserted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, WAIT is de-asserted.
Datasheet
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