28F128L30 データシートの表示（PDF） - Intel
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28F128L30 Datasheet PDF : 100 Pages
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28F640L30, 28F128L30, 28F256L30
Table 2.
Device Signal Descriptions for S-CSP (Sheet 2 of 2)
WP#
ADV#
R-UB#
R-LB#
RST#
P-Mode
VPP,
VPEN
VCC1
VCC2
S-VCC
P-VCC
VCCQ
VSS
RFU
DU
NC
Input
Input
Input
Input
Input
Power
Power
Power
Power
Power
Power
FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down
protection mechanism of the selected flash die. WP#-low enables the lock-down
mechanism - locked down blocks cannot be unlocked with software commands.
WP#-high disables the lock-down mechanism, allowing locked down blocks to be
unlocked with software commands.
FLASH ADDRESS VALID: Active-low input. During synchronous read operations,
addresses are latched on the rising edge of ADV#, or on the next valid CLK edge
with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or
continuously flows through if ADV# is held low.
RAM UPPER / LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low
enables the RAM high order bytes on D[15:8], and R-LB#-low enables the RAM low-
order bytes on D[7:0].
Treat this signal as NC (No Connect) for this device.
FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables
flash operations. RST#-high enables flash operation. Exit from reset places the flash
in asynchronous read array mode.
PSRAM MODE: Low-true; P-MODE is used to program the configuration register,
and enter/exit low power mode.
Treat this signal as NC (No Connect) for this device.
FLASH PROGRAM / ERASE POWER: A valid voltage on this pin allows erasing or
programming. Memory contents cannot be altered when VPP ≤ VPPLK. Block erase
and program at invalid VPP voltages should not be attempted.
Set VPP = VCC for in-system program and erase operations. To accommodate
resistor or diode drops from the system supply, the VIH level of VPP can be as low as
VPP1 min. VPP must remain above VPP1 min to perform in-system flash modification.
VPP may be 0 V during read operations.
VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter
blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to
exceed 80 hours. Extended use of this pin at 12 V may reduce block cycling
capability
VPEN ((Erase/Program/Block Lock Enables) is not available for L18/L30
products.
FLASH LOGIC POWER: VCC1 supplies power to the core logic of flash die #1;
VCC2 supplies power to the core logic of flash die #2. Write operations are inhibited
when VCC < VLKO. Device operations at invalid VCC voltages should not be
attempted.
SRAM POWER SUPPLY: Supplies power for SRAM operations.
Treat this signal as NC (No Connect) for this device.
PSRAM POWER SUPPLY: Supplies power for PSRAM operations.
Treat this signal as NC (No Connect) for this device.
FLASH I/O POWER: Supply power for the input and output buffers.
GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED for FUTURE USE: Reserve for future device functionality/
enhancements. Contact Intel regarding their future use.
DON’T USE: Do not connect to any other signal, or power supply; must be left
floating.
NO CONNECT: No internal connection; can be driven or floated.
14
Datasheet
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