28F256L18 データシートの表示（PDF） - Numonyx -> Micron
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28F256L18 Datasheet PDF : 106 Pages
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Numonyx™ StrataFlash® Wireless Memory (L18)
Revision History
Revision Date Revision
Description
10/15/02
01/20/03
04/11/03
08/04/03
01/20/04
05/22/04
09/02/04
09/29/04
04/22/05
-001
-002
-003
-004
-005
-006
-007
-008
-009
Initial Release
Revised 256-Mbit Partition Size
Revised 256-Mbit Memory Map
Change WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all
Writes)
Change WAIT function to active during Synchronous Non-Array Read
Updated all Waveforms to reflect new WAIT function
Revised Section 8.2.2
Added Synchronous Read to Write transition Section
Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns
Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22
Various text edits
Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing
Changed ICCS and ICCR values
Added 256-Mbit AC Speed
Changed Program and Erase Spec
Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow Chart
Revised Read While Buffered Programming Flow Chart
Revised Appendix A Write State Machine
Revised CFI Table 21 CFI Identification
Various text edits.
Various text clarifications, various text edits, block locking state diagram clarification, synchronous
read to write timing clarification, write to synchronous read timing clarification
Minor text edits
Changed Capacitance values
Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and
Automatic Power Savings Current (typ)
Updated Transient Equialent Testing Load Circuit
Added Table 19, “Bus Operations Summary” on page 42
Added the following order items:
* RD48F2000L0YTQ0, RD48F2000L0YBQ0
* RD48F4000L0YTQ0, RD48F4000L0YBQ0
* PF48F3000L0YTQ0, PF48F3000L0YBQ0
* PF48F4000L0YTQ0, PF48F4000L0YBQ0
* NZ48F4000L0YTQ0, NZ48F4000L0YBQ0
* JZ48F4000LOYTQ0, JZ48F4000LOYBQ0
Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm
Added mechanical drawing Figure 4, “256-Mbit, 88-ball (80-active ball) Drawing and Dimensions (8x11x1.0
mm)” on page 14
Corrected 256L18 package size from 8x10x1.2 mm to 8x11x1.2 mm in the Order information
table.
Removed Bin 2 LC and Frequency Support Tables
Added back VF BGA mechanical drawings
Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP
Updated Ordering Info
Minor text edits
Converted datasheet to new template
In Table 5, “Bottom Parameter Memory Map, 128-Mbit” on page 22, corrected 256-Mbit Blk 131 address
range from 100000 - 10FFFF to 800000 - 80FFFF
In Section 5.1, “Absolute Maximum Ratings” on page 23, corrected Voltage on any signal (except VCC,
VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V
In Section E.2, “Ordering Information for SCSP” on page 105, corrected package designators for leaded
and lead-free packages from RD/PF to NZ/JZ
Datasheet
6
November 2007
251902-12
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