28F256L30 データシートの表示（PDF） - Numonyx -> Micron
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28F256L30 Datasheet PDF : 102 Pages
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Numonyx™ StrataFlash® Wireless Memory (L30)
Table 1: Signal Descriptions for VF BGA Package (Sheet 2 of 2)
Symbol
Type
Name and Function
DU
NC
RFU
—
Do Not Use: Do not use this ball. This ball should not be connected to any power supplies, signals or
other balls, and must be left floating.
—
No Connect: No internal connection; can be driven or floated.
—
Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.
Table 2:
Symbol
A[Max:0]
DQ[15:0]
F1-CE#
F2-CE#
F3-CE#
S-CS1#
S-CS2
P-CS#
F1-OE#
F2-OE#
R-OE#
WE#
R-WE#
CLK
WAIT
Device Signal Descriptions for 128/0 and 256/0 SCSP (Sheet 1 of 2)
Type
Description
Input
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
• 128-Mbit Die: A[Max] = A22
• 256-Mbit Die: A[Max] = A23
Input/
Output
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles, outputs data during read
cycles. Data signals float when the device or its outputs are deselected. Data is internally latched
during writes.
Input
FLASH CHIP ENABLE: Low-true: selects the associated flash memory die. When asserted, flash
internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the
associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are
placed in high-Z state.
F1-CE# selects the flash die.
F2-CE# and F3-CE# are available on stacked combinations with two or three flash dies else they are
RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility.
Input
SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input
buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted
(S-CS1# = VIH or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
Input
PSRAM CHIP SELECT: Low-true; when asserted, PSRAM internal control logic, input buffers,
decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is
reduced to standby levels.
Treat this signal as NC (No Connect) for this device.
Input
FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the
flash output buffers, and places the flash outputs in High-Z.
F2-OE# is available on stacked combinations with two or three flash dies else it is RFU. It can be pulled
high to VCCQ through a 10K-ohm resistor for future design flexibility.
Input
RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the selected RAM output buffers. R-OE#-high
disables the RAM output buffers, and places the selected RAM outputs in High-Z.
Treat this signal as NC (No Connect) for this device.
Input FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data
are latched on the rising edge of WE#.
Input
RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die.
Treat this signal as NC (No Connect) for this device.
Input
FLASH CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode
and increments the internal address generator. During synchronous read operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs
first.
Output
FLASH WAIT: Indicates data valid in synchronous array or non-array burst reads. Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. With CE# and OE# at VIL, WAIT’s
active output is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
Datasheet
18
November 2007
Order Number: 251903-11
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