29C516E データシートの表示（PDF） - Atmel Corporation
部品番号
コンポーネント説明
メーカー
29C516E Datasheet PDF : 17 Pages
| |||
29C516E
Table 8:
Function
1
1
1
1
0
0
x
x
x
0
x
01
10
1
0
0
x
x
x
x
x0
1
x
1
xxxx
xx
x
1
1
x
x
1
0
0
x
1
1
1
x
x
x
1
0
0
0
x
01
11
x
x
x
1
0
0
x
x0
1xx
x
x
x
1
xx
x1
1
0
0
1
x
x
x
x : don’t care
9.2. Memory Write
The TRANS pin is driven at a high level to select the
access to the memory. The external arbiter drives the
U2/U1 pin and dispatches the commands RD/WRx,
Table 9:
1 UD1[0..15] = MD[0..15]
1 UD1[0..15] = {corrected MD[0..15]}
0 UD1[0..15] = {corrupted MD[0..15]}
UD1[0..15] = MD[0..15]
x
UD1[0..15] = {MC[0..7] Syndrome}
UD1[0..15] = H.Z
x
x UD2[0..15] = {expected UD1[0..15]} (User 2 listening)
1 UD2[0..15] = MD[0..15]
1 UD2[0..15] = {corrected MD[0..15]}
0 UD2[0..15] = {corrupted MD[0..15]}
UD2[0..15] = MD[0..15]
x
UD2[0..15] = {MC[0..7] Syndrome}
UD2[0..15] = H.Z
x
x UD1[0..15] = {expected UD2[0..15]} (User 1 listening)
MEMx and ENx. All transaction managed by the master
user can be listened by the second user.
Function
0
0
0
x
x
x
MD[0..15] = UD1[0..15]
MC[0..7] = {check–bits generated from UD1[0..15]}
1
0
1
x
MD[0..15] = H.Z
0
x
x
x
x
1
MC[0..7] = H.Z
0
x
x
1
0
0 UD2[0..15] = UD1[0..15] (User 2 listening)
x
x
x
0
0
0
MD[0..15] = UD2[0..15]
MC[0..7] = {check–bits generated from UD2[0..15]}
1
1
1
x MD[0..15] = H.Z
x
x
x
0
x
1 MC[0..7] = H.Z
1
0
0
0
x
x UD1[0..15] = UD2[0..15] (User 1 listening)
x : don’t care
CERR and NCERR are not valid
CORRECT and SYNCHK are not active
10
Rev. E (03 2007)
Share Link: 