VSC8131 データシートの表示（PDF） - Vitesse Semiconductor

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VSC8131

2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8131

2.488 Gbit/sec

32:1 SONET/SDH Mux with Clock Generator

High Speed Data Output

The high speed data will be multiplexed in the sequence D0, D1 up to D31 with D0 being transmitted first.

The high speed data output driver consists of a differential pair designed to drive a 50Ω transmission line. The

transmission line should be terminated with a 100Ω resistor at the load between the true and complement out-

puts, refer to Figure 2. No connection to a termination voltage is required. The output driver is back terminated

to 50Ω on-chip, providing snubbing of any reflections. If used single-ended, the high speed output driver must

still be terminated differentially at the load with a 100Ω resistor between the true and complement output sig-

nals.

High Speed Clock Output

The high speed clock output driver consists of a differential pair designed to drive a 50Ω transmission line.

The transmission line should be terminated with a 100Ω resistor at the load between the true and complement

output, refer to Figure 2. No connection to a termination voltage is required. The output driver is back termi-

nated to 50Ω on-chip, providing a snubbing of any reflections. If used single-ended, the high speed output

driver must still be terminated differentially at the load with a 100Ω resistor between the true and complement

output signals.

Figure 2: Termination for High Speed Clock and Data Output Drivers

VCC

50Ω

Pre-Driver

50Ω

100Ω

Z0 = 50Ω

VEE

G52249-0, Rev. 3.0

11/9/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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