HFA3683A データシートの表示（PDF） - Intersil
部品番号
コンポーネント説明
メーカー
HFA3683A Datasheet PDF : 17 Pages
| |||
HFA3683A
PLL Synthesizer Table
REGISTER
DEFINITION
SERIAL BITS LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R Counter
0
0 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) X (Don’t Care)
A/B Counter 0
1 A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10)
Operational
1
0 M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0 0 0 0 M(13) M(14) M(15) X X
Mode
Reference Frequency Counter/Divider
BIT
DESCRIPTION
R(0-14)
Least significant bit R(0) to most significant bit R(14) of the divide by R counter. The Reference signal frequency is divided down
by this counter and is compared with a divided LO by a phase detector.
LO Frequency Counters/Dividers
BIT
DESCRIPTION
A(0-6)
B(0-11)
Least significant bit A(0) to most significant bit A(6) of a 7-bit Swallow counter and LSB B(0) to MSB B(10) of the 11-bit divider.
The LO frequency is divided down by [P*B+A], where P is the Prescaler divider set by bit M(2). This divided signal frequency is
compared by a phase detector with the divided Reference signal.
Operational Modes
BIT
DESCRIPTION
M(0)
(PLL_PE), Phase Lock Loop Power Enable. 1 = Enable, 0 = Power Down. Serial port always on.
M(2)
Prescaler Select. 0 = 32/33, 1 = 64/65
M(3)
M(4)
Charge Pump Current Setting
M(4)
0
M(3)
0
OUTPUT SINK/SOURCE
0.25mA
0
1
0.50mA
1
0
0.75mA
1
1
1.00mA
M(5)
M(6)
Charge Pump Sign
M(7)
M(8)
M(13)
LD Pin Multiplex Operation
M(6)
0
0
M(13)
0
0
M(5)
0
1
M(8)
0
1
Source Current if LO/ [P*B+A] < Ref/R
Source Current if LO/ [P*B+A] > Ref/R
M(7)
OUTPUT AT PIN LD
X
Lock Detect Operation
X
Short to GND
1
0
X
Serial Register Read Back
1
1
0
Ref. Divided by R Waveform
1
1
1
LO Divided by [P*B+A]
Waveform
M(14)
M(15)
Charge Pump Operation/Test
M(15)
0
M(14)
0
OPERATION/TEST
Normal Operation
0
1
Charge Pump Constant Current Source
1
0
Charge Pump Constant Current Sink
1
1
High Impedance State
2-7
Share Link: 