A65H83181P-6 データシートの表示（PDF） - AMIC Technology

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A65H83181P-6

128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output

AMIC Technology 

Block Diagram

A65H73361/A65H83181 Series

SA0-SA17

CK

SS

Latch

ZZ

SW

SBW

Latch

RD Add

Register

SW

Register

SW

Register

SBW

Register

SBW

Register

WR Add

Register

128Kx36

or

256Kx18

Array

Column Decoder

Read/Write Amp

2:1 MUX

Write

Buffer

SS

Register

SS

Register

Data Out

Registor

G

DQ0 - DQ35

Pin Description

SA0-SA17

DQ0-DQ35

CK , CK

Address input

(X18 : SA0 - SA17, X36 : SA0 - SA16)

Data I/O

(X18 : DQ0 - DQ17, X36 : DQ0 - DQ35)

Differential input register clocks

SW

Write enable. Global

SBWa

Write enable. Byte a (DQ0-DQ8)

SBWb

Write enable. Byte b (DQ9-DQ17)

SBWc

Write enable. Byte c (DQ18-DQ26)

SBWd

Write enable. Byte d (DQ27-DQ35)

TMS, TDI, TCK IEEE 1149.1 test inputs(LVTTL levels)

TDO

IEEE 1149.1 test output(LVTTL level)

G

Asynchronous output enable

SS

Synchronous select

M1, M2 For boundary scan purpose

VREP(2) HSTL input reference voltage

VDD

Power supply (+3.3V)

VSS

Ground

VDDQ

Output power supply

ZZ

Asynchronous sleep mode

ZQ

Output driver impedance control

NC

No connect

PRELIMINARY (February, 1999, Version 2.0)

3

AMIC Technology, Inc.

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