L6260 データシートの表示（PDF） - STMicroelectronics
部品番号
コンポーネント説明
メーカー
L6260 Datasheet PDF : 30 Pages
| |||
L6260
PIN DESCRIPTION (continued)
Pin Types: I = Input, O = Output, P = Power, A = Analog (passive)
Power down sequencing, POR, other voltage pins
PIN #
13
28
30
61
62
64
2
52
5
50
51
4
3
PIN NAME
DESCRIPTION
VRECT
BRK_DLY
VPDOWN
C1HIGH
C1LOW
C2HIGH
C2LOW
POR_DLY
POR
UV1
SPN_DSBL_
DLY
VHTRIP
VLTRIP
Output of the synchronous rectifier supplying power to
the retract circuitry. Filtered by an internal 400pF
capacitor. Normally not externally connected. However,
if retract command is to be used, a small signal silicon
diode must be connected between this pin and Vcc
(Cathode to VRECT) to supply the additional current
which may be required to brake the VCM.
An external parallel RC network from this point to
ground sets the Brake dELAY:T = 0.45 RC.
Typical values are R = 4MΩ, C=0.1µF (0.16sec,
delay).
Voltage tripler reservoir capacitor. This is used for
the brake operation when power is removed from
the chip. No DC load allowed. 1µF minimum, 10µF
prefered.
Positive terminal of charge pump capacitor.
10nF (typ) for Tripler operation;
330nF (typ0 or Doubler operation
Negative terminal of charge pump capacitor.
10nF (typ) for Tripler operation;
330nF (typ) or Doubler operation
Positive terminal of charge pump capacitor for
Tripler operation. 330nF (typ).
Connected tp VHRTRIP for Doubler operation.
Negative terminal of charge pump capacitor for
Tripler operation. 330nF (typ).
Not connected for Doubler operation.
An external capacitor from this pin to ground sets
the duration of POR after power has been re-
established. T (por) = 32 X C (por)
where: C (por) is in pF and T is expresssed in µs.
Power On Reset. This open drain output goes low
when the voltage at either UV1 or UV2 goes below
1.25V.
Under voltage detector 1. This defines the
VOLTAGE GOOD threshold by comparing the
voltage on this pin to the internal 1.25V reference.
An external resistor divider network and capacitor
filter provides the selection of threshold and supply
noise rejection. There is an internal pull-up (2µA
max). Hysteresis is 20mV.
Spindle Disable Delay . A capacitor connected
between this pin and Vcc programs the delay
between POR and the disabling of the Spindle
section..
Delay = 80 xC (C in pF; Delay in µs)
High tripler/Doubler output. 330nF (typ). 11V max.
Low tripler/Doubler output. 330nF (typ). for stability.
PIN
I\O
TRI-STATE
TYPE MAPPED? @SLEEP/@POR
AO
No
No
A
No
No
A
No
No
A
No
No
A
No
No
A
No
No
A
No
No
A
No
No
DO
Yes
No
AI
Yes
No
AI
Yes
No
AO
No
No
AO
No
No
5/30
Share Link: 