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A3974 データシートの表示(PDF) - Allegro MicroSystems

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A3974
Allegro
Allegro MicroSystems Allegro
A3974 Datasheet PDF : 12 Pages
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3974
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
D14 Enable Logic. This bit, in conjuction with ENABLE,
determines if the output drivers are in the chopped or on state.
ENABLE1 D14
0
0
1
0
0
1
1
1
Mode
Chopped
On
On
Chopped
D15 Phase Logic. This bit determines if the device is
operating in the forward or reverse state.
D15
State
OUTA OUTB
0
Reverse
L
H
1
Forward
H
L
D16 Gm Range Select. This bit determines if VREF is divided
by 5 or 10.
D16
Divider
0
÷10
1
÷5
Word 1 Bit Assignments
Select Word 1 (D18 = 1)
Bit
Function
D0
Bridge 2 blank time LSB
D1
Bridge 2 blank time MSB
D2
Bridge 2 off-time LSB
D3
Bridge 2 off-time bit 1
D4
Bridge 2 off-time bit 2
D5
Bridge 2 off-time bit 3
D6
Bridge 2 off-time MSB
D7
Bridge 2 fast-decay time bit LSB
D8
Bridge 2 fast-decay time bit 1
D9
Bridge 2 fast-decay time bit 2
D10
Bridge 2 fast-decay time bit MSB
D11
Bridge 2 sync. rect. control
D12
Bridge 2 sync. rect. control
D13
Bridge 2 external PWM mode
D14
Bridge 2 enable
D15
Bridge 2 phase
D16
Bridge 2 reference range select
D17
Bridge 2 internal PWM mode
D18
Word select = 1
D19
Idle mode
D17 Bridge 2 Mode. This bit determines slow or mixed
decay for internal current-control operation.
D17
Decay Mode
0
Mixed
1
Slow
D19 Test Mode. This bit is reserved for testing and should
never be changed by the user. Default (low) operates the
device in normal mode.
D0 - D17. Identical definitions as Word 0, with Word 1
selected. Data is written to Full Bridge 2.
D19 Idle Mode. The device can be placed in a low-power
“idle” mode by writing a “0” to D19. The outputs will be
disabled, the charge pump will be turned off, and the device
will draw a lower load supply currrent. The undervoltage
monitor circuit will remain active. D19 should be programmed
high for 1 ms before attempting to enable any output driver.
continued next page ...
6
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