3D7418S-3 データシートの表示（PDF） - Data Delay Devices
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3D7418S-3 Datasheet PDF : 7 Pages
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3D7418
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
VDD
-0.3
7.0
V
Input Pin Voltage
VIN
-0.3
VDD+0.3
V
Input Pin Current
IIN
-10
10
mA
25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300
C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
Input Threshold Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
IDD
VTH
IIH
IIL
IOH
Low Level Output Current
IOL
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = CLD * VDD * F
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
MIN MAX UNITS NOTES
1.0
3.0
mA
2.2
2.8
V
1.0
µA
VIH = VDD
1.0
µA
VIL = 0V
-4.0
mA VDD = 4.75V
VOH = 4.0V
4.0
mA VDD = 4.75V
VOL = 0.4V
2
ns
CLD = 5 pf
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
NOTES
Clock Frequency
fC
80
MHz
Enable Width
tEW
10
ns
Clock Width
tCW
10
ns
Data Setup to Clock
tDSC
10
ns
Data Hold from Clock
tDHC
3
ns
Data Setup to Enable
tDSE
10
ns
Data Hold from Enable
tDHE
3
ns
Enable to Serial Output Valid
tEQV
20
ns
Enable to Serial Output High-Z
tEQZ
20
ns
Clock to Serial Output Valid
tCQV
20
ns
Clock to Serial Output Invalid
tCQX
10
ns
Enable Setup to Clock
tES
10
ns
Enable Hold from Clock
tEH
10
ns
Parallel Input Valid to Delay Valid
tPDV
20 40
ns
1
Parallel Input Change to Delay Invalid
tPDX
0
ns
1
Enable to Delay Valid
tEDV
35 45
ns
1
Enable to Delay Invalid
tEDX
0
ns
1
Input Pulse Width
tWI
8
% of Total Delay See Table 1
Input Period
Period 20
% of Total Delay See Table 1
Input to Output Delay
tPLH, tPHL
ns
See Table 2
NOTES: 1 - Refer to PROGRAMMED DELAY (ADDRESS) UPDATE section
Doc #02005
DATA DELAY DEVICES, INC.
6
6/17/02
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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