48SD3208 データシートの表示（PDF） - MAXWELL TECHNOLOGIES

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48SD3208

256 Mb SDRAM 8-Meg X 8-Bit X 4-Banks

MAXWELL TECHNOLOGIES 

256Mb (8-Meg X 8-Bit X 4-Banks) SDRAM

48SD3208

DQM Truth Table

COMMAND

Byte (DQ0 to DQ7) write enable/output enable

Byte (DQ0 to DQ7) write inhibit/output disable

SYMBOL

ENBL

MASK

CKE= N-1

H

H

CKE = N

x

x

DQM

L

H

Note: H: VIH L: VIL x VIH or VIL

Write: IDID is Needed

Read: IDOD is Needed

The SDRAM can mask input/output data by means of DQM.

During reading, the output buffer is set to Low-Z by setting DQM to Low, enabling data output. On the other

hand, when DQM is set High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQM to Low. When DQM is set to High, the previous data is held

( the new data is not written). Desired data can be masked during burst read or burst write by setting DQM..

For more details, refer to the DQM control section of the SDRAM operating instructions.

CKE Truth Table

CURRENT STATE

COMMAND

N-1

N

CS

RAS CAS

WE ADDRESS

Active

Clock suspended mode entry

H

L

x

x

x

x

x

Any

Clock Suspend

L

L

x

x

x

x

x

Clock Suspend Clock Suspend mode exit

L

H

x

x

x

x

x

Idle

Auto-refresh command (REF)

H

H

L

L

L

H

x

Idle

Self-refresh entry (SELF)

H

L

L

L

L

H

x

Idle

Power down entry

H

L

L

H

H

H

x

H

L

HL

x

x

x

x

Self Refresh

Self Refresh exit (SELFX)

L

H

L

H

H

H

x

Power down

Power down exit

L

H

L

H

H

H

x

L

H

H

x

x

x

x

Note: H:VIH L:VIL x VIH or VIL

Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to

Low. If a command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend

mode change depending on the current status (1 clock before) as described below.

01.10.05 Rev 2

All data sheets are subject to change without notice 10

©2005 Maxwell Technologies

All rights reserved.

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