AS4LC1M16883C データシートの表示（PDF） - Austin Semiconductor
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AS4LC1M16883C Datasheet PDF : 22 Pages
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NOTE:
AUSTIN SEMICONDUCTOR, INC.
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
READ CYCLE
tRC
tRAS
tRP
V IH
RAS VIL
tCRP
tRCD
tCSH
tRSH
tCAS
tCLCH
tRRH
CASL/CASH VVIIHL
,,,,,,,,,,,, ,,,,, ADDR
VV IIHL
, ,,,,,, WE VVIIHL
, , DQ
V
V
OH
OL
,,,,,,,,,,,,,,,,,,,,,,,,,, OE
VV IIHL
tASR
tRAD
tRAH
ROW
tWRP tWRH
NOTE 1
OPEN
tAR
tASC
tRAL
tCAH
tACH
tRCS
COLUMN
tRCH
tAA
tRAC
tCAC
tCLZ
t OE
NOTE 2
tOFF
VALID DATA
t OD
ROW
OPEN
DON’T CARE
UNDEFINED
1. Although ?W/E is a “don’t care” at ?R?A/S time during an access cycle (READ or WRITE), the system designer should implement
?W/E HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2. tOFF is referenced from rising edge of ?R?A/S or ?C?A/S, whichever occurs last.
TIMING PARAMETERS
SYM
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLCH
tCLZ
tCRP
tCSH
tOD
tOE
tOFF
-6
MIN MAX
30
15
45
0
0
15
10
12 10,000
10
0
5
50
0
15
15
0
15
-7
MIN MAX
35
15
50
0
0
20
12
13 10,000
10
0
5
55
0
15
20
0
15
-8
MIN MAX
40
20
60
0
0
20
15
20 10,000
10
0
5
60
0
20
20
0
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
tRAC
tRAD
tRAH
tRAL
tRAS
tRC
tRCD
tRCH
tRCS
tRP
tRRH
tRSH
tWRH
tWRP
-6
MIN MAX
60
12 30
10
30
60 10,000
110
14 45
0
0
40
0
13
10
10
-7
MIN MAX
70
12 35
10
35
70 10,000
130
14 50
0
0
50
0
15
10
10
-8
MIN MAX
80
15 40
10
40
80 10,000
150
20 60
0
0
60
0
15
10
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS4LC1M16
REV. 3/97
DS000020
2-103
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
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