SN74LS196 データシートの表示（PDF） - Motorola => Freescale
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SN74LS196 Datasheet PDF : 6 Pages
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SN54/74LS196 • SN54/74LS197
FUNCTIONAL DESCRIPTION
The LS196 and LS197 are asynchronously presettable de-
cade and binary ripple counters. The LS196 Decade Counter
is partitioned into divide-by-two and divide-by-five sections
while the LS197 is partitioned into divide-by-two and divide-
by-eight sections, with all sections having a separate Clock in-
put. In the counting modes, state changes are initiated by the
HIGH to LOW transition of the clock signals. State changes of
the Q outputs, however, do not occur simultaneously because
of the internal ripple delays. When using external logic to de-
code the Q outputs, designers should bear in mind that the un-
equal delays can lead to decoding spikes and thus a decoded
signal should not be used as a clock or strobe. The CP0 input
serves the Q0 flip-flop in both circuit types while the CP1 input
serves the divide-by-five or divide-by-eight section. The Q0
output is designed and specified to drive the rated fan-out plus
the CP1 input. With the input frequency connected to CP0 and
Q0 driving CP1, the LS197 forms a straightforward module-16
counter, with Q0 the least significant output and Q3 the most
significant output.
The LS196 Decade Counter can be connected up to oper-
ate in two different count sequences, as indicated in the tables
of Figure 2. With the input frequency connected to CP0 and
with Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)
sequence. With the input frequency connected to CP1 and Q3
driving CP0, Q0 becomes the low frequency output and has a
50% duty cycle waveform. Note that the maximum counting
rate is reduced in the latter (bi-quinary) configuration because
of the interstage gating delay within the divide-by-five section.
The LS196 and LS197 have an asynchronous active LOW
Master Reset input (MR) which overrides all other inputs and
forces all outputs LOW. The counters are also asynchronously
presettable. A LOW on the Parallel Load input (PL) overrides
the clock inputs and loads the data from Parallel Data (P0 – P3)
inputs into the flip-flops. While PL is LOW, the counters act as
transparent latches and any change in the Pn inputs will be re-
flected in the outputs.
Figure 2. LS196 COUNT SEQUENCES
DECADE (NOTE 1)
BI-QUINARY (NOTE 2)
COUNT
Q3
Q2
Q1
Q0
COUNT
Q0
Q3
Q2
Q1
0
L
L
L
L
0
L
L
L
L
1
L
L
L
H
1
L
L
L
H
2
L
L
H
L
2
L
L
H
L
3
L
L
H
H
3
L
L
H
H
4
L
H
L
L
4
L
H
L
L
5
L
H
L
H
5
H
L
L
L
6
L
H
H
L
6
H
L
L
H
7
L
H
H
H
7
H
L
H
L
8
H
L
L
L
8
H
L
H
H
9
H
L
L
H
9
H
H
L
L
NOTES:
1. Signal applied to CP0, Q0 connected to CP1.
2. Signal applied to CP1, Q3 connected to CP0.
MODE SELECT TABLE
INPUTS
MR
PL
CP
RESPONSE
L
X
X
H
L
X
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= HIGH to Low Clock Transition
Reset (Clear)
Parallel Load
Count
FAST AND LS TTL DATA
5-3
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