PDM31034SA10SO データシートの表示（PDF） - Paradigm Technology
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PDM31034SA10SO Datasheet PDF : 8 Pages
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PRELIMINARY
PDM31034
Write Cycle No. 3 (Chip Enable Controlled)
tWC
1
ADDR
tAW
tAH
tAS
tCW
2
CE
WE
DIN
DOUT
tWP
3
tDS
tDH
DATA VALID
4
HIGH-Z
NOTE: Output Enable (OE) is inactive (high)
5
AC Electrical Characteristics
Description
-9
-10
-12
-15
-20
WRITE Cycle
WRITE cycle time
Chip enable active time
Address valid to end of write
Address setup time
Address hold from end of write
Write pulse width
Data setup time
Data hold time
Write disable to output in low Z(1,3)
Write enable to output in high Z(1,3)
Sym
tWC
tCW
tAW
tAS
tAH
tWP
tDS
tDH
tLZWE
tHZWE
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
9
10
12
15
20
ns
8
9
10
11
12
ns
8
9
10
11
12
ns
0
0
0
0
0
ns
0
0
0
0
0
ns
7
8
9
10
11
ns
5
6
7
8
9
ns
0
0
0
0
0
ns
0
0
0
0
0
ns
6
7
7
8
9 ns
6
7
8
9
10
NOTES: (For two previous Electrical Characteristics tables)
11
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
3. This parameter is sampled.
4. WE is high for a READ cycle.
5. The device is continuously selected. Chip Enable is held in their active state.
12
6. The address is valid prior to or coincident with the latest occuring Chip Enable.
Rev. 1.3
7
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