56F8013 データシートの表示（PDF） - Freescale Semiconductor

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56F8013

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8013/56F8011 Signal Pins

Table 2-3 56F8013/56F8011 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal LQFP

Name Pin No.

Type

State During

Reset

Signal Description

GPIOB7

3

(TXD)

(SCL2)

Input/

Output

Output

Input/

Output

Input with

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

Transmit Data — SCI transmit data output or transmit / receive in

single wire operation.

Serial Clock — This pin serves as the I2C serial clock.

After reset, the default state is GPIOB7. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

2. This signal is also brought out on the GPIOB0 pin.

RESET

15

Input

Input with

internal

pull-up

enabled

Reset — This input is a direct hardware reset on the processor.

When RESET is asserted low, the chip is initialized and placed in the

reset state. A Schmitt trigger input is used for noise immunity. The

internal reset signal will be deasserted synchronous with the internal

clocks after a fixed number of internal clocks.

(GPIOA7)

Input/Open

Drain

Output

Port A GPIO — This GPIO pin can be individually programmed as

an input or open drain output pin. Note that RESET functionality is

disabled in this mode and the chip can only be reset via POR, COP

reset, or software reset.

After reset, the default state is RESET.

GPIOB4

19

(T0)

Input/

Output

Input/

Output

Input with

internal

pull-up

enabled

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

T0 — Timer, Channel 0

(CLKO)

Output

Clock Output — This is a buffered clock signal. Using the

SIM_CLKO Select Register (SIM_CLKOSR), this pin can be

programmed as any of the following: disabled (logic 0), CLK_MSTR

(system clock), IPBus clock, or oscillator output. See Section 6.3.7.

After reset, the default state is GPIOB4. The alternative peripheral

functionality is controlled via the SIM. See Section 6.3.8.

Return to Table 2-2

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

19

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