56F801XBLUG データシートの表示（PDF） - Freescale Semiconductor

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56F801XBLUG

16-bit Digital Signal Controllers

Freescale Semiconductor 

Award-Winning Development Environment

1.3 Award-Winning Development Environment

Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use

component-based software application creation with an expert knowledge system.

The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,

compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and

development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs

create a complete, scalable tools solution for easy, fast, and efficient development.

1.4 Architecture Block Diagram

The 56F8013/56F8011’s architecture is shown in Figure 1-1, Figure 1-2, and Figure 1-3. Figure 1-1

illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and

the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and

control blocks connected to the IPBus Bridge. Figure 1-3 details how the device’s I/O pins are muxed.

The figures do not show the on-board regulator and power and ground signals. Please see Part 2,

Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals.

1.5 Synchronize ADC with PWM

ADC conversion can be synchronized with PWM module via Quad Timer channel 2 and 3 if needed.

Internally, the PWM synch signal, which is generated at every PWM reload, can be connected to the timer

channel 3 input and the timer channel 2 and 3 outputs are connected to ADC sync inputs. Timer channel

3 output is connected to SYNC0 and Timer channel 2 is connected to SYNC1. The setting is controlled by

TC3_INP bit in the SIM Control Register; see Section 6.3.1.

SYNC0 is the master ADC sync input is used to trigger both ADCA and ADCB in sequence and parallel

mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger

ADCA. See 56F801X Peripheral Reference Manual for additional information.

1.6 Multiple Frequency PWM

When both PWM channels of a complementary pair in software control mode and software control bits

are set to 1, each complementary PWM signal pair—PWM 0 and 1; PWM 2 and 3; PWM 4 and 5—can

select a PWM source of one of following sources that enables each PWM pair to output different frequency

PWM signal.

• External GPIO input:

— GPIOB2 input can be used to drive PWM 0 and 1

— GPIOB3 input can be used to drive PWM 2 and 3

— GPIOB4 input can be used to drive PWM 4 and 5

• Quad Timer output:

— Timer0 output can be used to drive PWM 0 and 1

56F8013/56F8011 Data Sheet, Rev. 12

Freescale Semiconductor

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