DSP56F802TA80(2005) データシートの表示（PDF） - Freescale Semiconductor

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DSP56F802TA80
(Rev.:2005)

16-bit Digital Signal Controllers

Freescale Semiconductor 

JTAG/OnCE

2.8 JTAG/OnCE

Table 2-10 JTAG/On-Chip Emulation (OnCE) Signals

No. of Signal Signal State During

Pins Name Type

Reset

Signal Description

1

TCK

Input Input, pulled Test Clock Input—This input pin provides a gated clock to synchronize the

(Schmitt) low internally test logic and shift serial data to the JTAG/OnCE port. The pin is connected

internally to a pull-down resistor.

1

TMS Input Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG TAP

(Schmitt) high internally controller’s state machine. It is sampled on the rising edge of TCK and has an

on-chip pull-up resistor.

1

TDI

Input Input, pulled Test Data Input—This input pin provides a serial input data stream to the

(Schmitt) high internally JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip

pull-up resistor.

1

TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data

stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR

controller states, and changes on the falling edge of TCK.

1

TRST Input Input, pulled Test Reset—As an input, a low signal on this pin provides a reset signal to the

(Schmitt) high internally JTAG TAP controller. To ensure complete hardware reset, TRST should be

asserted at power-up and whenever RESET is asserted. The only exception

occurs in a debugging environment, since the OnCE/JTAG module is under

the control of the debugger. In this case it is not necessary to assert TRST

when asserting RESET. Outside of a debugging environment RESET should

be permanently asserted by grounding the signal, thus disabling the

OnCE/JTAG module on the device.

56F802 Technical Data, Rev. 7

Freescale Semiconductor

13

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