DSP56F802TA80(2005) データシートの表示（PDF） - Freescale Semiconductor
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DSP56F802TA80 Datasheet PDF : 40 Pages
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9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless
the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up,
this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally
regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates.
160
120
IDD Digital IDD Analog IDD Total
80
40
0
10
20
30
40
50
60
70
80
Freq. (MHz)
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
VIH
Low
Input Signal
Midpoint1
Fall Time
VIL
High
Rise Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 3-2 Input Signal Measurement References
90%
50%
10%
56F802 Technical Data, Rev. 7
18
Freescale Semiconductor
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