56F803 データシートの表示（PDF） - Freescale Semiconductor

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56F803

16-bit Digital Signal Controllers

Freescale Semiconductor 

Pulse Width Modulator (PWM) Signals

Table 2-9 Interrupt and Program Control Signals (Continued)

No. of

Pins

1

Signal

Name

RESET

Signal

Type

Input

(Schmitt)

State During

Reset

Input

Signal Description

Reset—This input is a direct hardware reset on the processor.

When RESET is asserted low, the controller is initialized and placed

in the Reset state. A Schmitt trigger input is used for noise immunity.

When the RESET pin is deasserted, the initial chip operating mode

is latched from the EXTBOOT pin. The internal reset signal will be

deasserted synchronous with the internal clocks, after a fixed

number of internal clocks.

1

EXTBOOT

Input

(Schmitt)

Input

To ensure a complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware device reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case, assert

RESET, but do not assert TRST.

External Boot—This input is tied to VDD to force device to boot from

off-chip memory. Otherwise, it is tied to VSS.

2.6 Pulse Width Modulator (PWM) Signals

Table 2-10 Pulse Width Modulator (PWMA) Signals

No. of

Pins

Signal

Name

Signal State During

Type

Reset

Signal Description

6

PWMA0–5 Output

Tri-stated PWMA0–5— These are six PWMA output pins.

3

ISA0–2

Input

(Schmitt)

3 FAULTA0–2 Input

(Schmitt)

Input

Input

ISA0–2— These three input current status pins are used for

top/bottom pulse width correction in complementary channel

operation for PWMA.

FAULTA0–2— These three fault input pins are used for disabling

selected PWMA outputs in cases where fault conditions originate

off-chip.

56F803 Technical Data, Rev. 16

Freescale Semiconductor

13

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