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56F803 データシートの表示(PDF) - Freescale Semiconductor

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56F803
Freescale
Freescale Semiconductor Freescale
56F803 Datasheet PDF : 52 Pages
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56F803 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Program RAM
• 4K × 16-bit words (8KB) Data Flash
• 2K × 16-bit words (4KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• Up to 64K × 16-bit words each of external Program
and Data memory
• 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 16 shared GPIO lines
• 100–pin LQFP package
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
3
PWMA
A/D1
4
A/D2 ADC
4
VREF
Quadrature
Decoder 0 /
4
Quad Timer A
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Quad Timer B
Boot Flash
2048 x 16 Flash
Quad Timer C
Quad Timer D
Data Memory
4096 x 16 Flash
2
2048 x 16 SRAM
CAN 2.0A/B
2
SCI
or
2
GPIO
COP/
Watchdog
Applica-
SPI
tion-Specific
4
or
GPIO
Memory &
Peripherals
EXTBOOT
RESET
IRQB
IRQA
6
JTAG/
OnCE
Port
VCAPC VDD VSS VDDA
2
6
6*
VSSA
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
••
PAB
PDB
XDB2
CGDB
XAB1
XAB2
INTERRUPT
IPBB
CONTROLS CONTROLS
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
56F803 Block Diagram
16-Bit
56800
Core
PLL
Clock Gen
CLKO
XTAL
EXTAL
External 6
Address Bus
A[00:05]
A[06:15] or
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
GPIO-E2:E3 &
10 GPIO-A0:A7
D[00:15]
16
PS Select
Bus
DS Select
Control
WR Enable
RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
56F803 Technical Data, Rev. 16
Freescale Semiconductor
3

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