56F8135 データシートの表示（PDF） - Freescale Semiconductor

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56F8135

16-bit Digital Signal Controller

Freescale Semiconductor 

Table 1-2 Bus Signal Names

Name

Function

Program Memory Interface

pdb_m[15:0] Program data bus for instruction word fetches or read operations.

cdbw[15:0]

Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are

used for writes to program memory.)

pab[20:0]

Program memory address bus. Data is returned on pdb_m bus.

Primary Data Memory Interface Bus

cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus.

xab1[23:0]

Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on

cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

Secondary Data Memory Interface

xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

xab2[23:0]

Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing

only words. Data is returned on xdb2_m.

Peripheral Interface Bus

IPBus [15:0]

Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as

the Primary Data Memory and therefore generates no delays when accessing the processor.

Write data is obtained from cdbw. Read data is provided to cdbr_m.

1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.

1.5 Product Documentation

The documents listed in Table 1-3 are required for a complete description and proper design with the

56F8335 and 56F8135 devices. Documentation is available from local Freescale distributors, Freescale

semiconductor sales offices, Freescale Literature Distribution Centers, or online at

http://www.freescale.com.

Topic

DSP56800E

Reference Manual

56F8300 Peripheral User

Manual

56F8300 SCI/CAN

Bootloader User Manual

56F8335/56F8135

Technical Data Sheet

Errata

Table 1-3 Chip Documentation

Description

Detailed description of the 56800E family architecture,

16-bit hybrid controller core processor, and the

instruction set

Detailed description of peripherals of the 56F8300

family of devices

Detailed description of the SCI/CAN Bootloaders

56F8300 family of devices

Electrical and timing specifications, pin descriptions,

device specific peripheral information and package

descriptions (this document)

Details any chip issues that might be present

Order Number

DSP56800ERM

MC56F8300UM

MC56F83xxBLUM

MC56F8335

MC56F8335E

MC56F8135E

56F8335 Technical Data, Rev. 1

12

Freescale Semiconductor

Preliminary

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