A6B273KLWTR-T データシートの表示（PDF） - Allegro MicroSystems
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A6B273KLWTR-T Datasheet PDF : 10 Pages
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6B273
8-BIT LATCHED
DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
STROBE
OUTPUTx
50%
t su(D) t h(D)
50%
50%
t su(D) t h(D)
t PLH
t PHL
90%
10%
tr
tf
Dwg. WP-036-1
Input Active Time Before Strobe
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Input Active Time After Strobe
(Data Hold Time), th(D) ................................................... 20 ns
Input Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VCC
Input Logic Low, VIL ................................................. ≤ 0.15VCC
INPUT
IO
VO
TEST CIRCUITS
+15 V
tav
IAS = 500 mA
DUT
V(BR)DSX
VO(ON)
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
OUT
Dwg. EP-066
www.allegromicro.com
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