73K222AL-IHR データシートの表示（PDF） - Teridian Semiconductor Corporation

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73K222AL-IHR

V.22, V.21, Bell 212A, 103 Single-Chip Modem

Teridian Semiconductor Corporation 

73K222AL

V.22, V.21, Bell 212A, 103

Single-Chip Modem

DATA SHEET

PARALLEL MICROPROCESSOR INTERFACE (continued)

NAME

WR

28-PIN

13

TYPE

I

DESCRIPTION

Write. A low on this informs the 73K222AL that data is available on

AD0-AD7 for writing into an internal register. Data is latched on the

rising edge of WR. No data is written unless both WR and the latched

CS are low.

SERIAL MICROPROCESSOR INTERFACE

A0-A2

-

I

Register Address Selection. These lines carry register addresses and

should be valid during any read or write operation.

DATA

-

I/O Serial Control Data. Data for a read/write operation is clocked in or out

on the falling edge of the EXCLK pin. The direction of data flow is

controlled by the RD pin. RD low outputs data. RD high inputs data.

RD

-

I

Read. A low on this input informs the 73K222AL that data or status

information is being read by the processor. The falling edge of the RD

signal will initiate a read from the addressed register. The RD signal

must continue for eight falling edges of EXCLK in order to read all eight

bits of the referenced register. Read data is provided LSB first. Data

will not be output unless the RD signal is active.

WR

-

I

Write. A low on this input informs the 73K222AL that data or status

information has been shifted in through the DATA pin and is available

for writing to an internal register. The normal procedure for a write is to

shift in data LSB first on the DATA pin for eight consecutive falling

edges of EXCLK and then to pulse WR low. Data is written on the

rising edge of WR.

NOTE: The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes

DATA and AD0, AD1 and AD2 become the address only. See timing diagrams on page 20.

Page: 5 of 27

© 2007 TERIDIAN Semiconductor Corporation

Rev 6.1

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