73K324BL-IHR データシートの表示（PDF） - Teridian Semiconductor Corporation
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73K324BL-IHR
Teridian Semiconductor Corporation
73K324BL-IHR Datasheet PDF : 34 Pages
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REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the AD0, AD1 and AD2 lines in serial mode, or in
parallel mode. The address lines and CS are latched
by ALE in the parallel mode. Register CR0 controls
the method by which data is transferred over the
phone line. CR1 controls the interface between the
microprocessor and the 73K324BL internal state.
DR is a detect register which provides an indication
73K324BL
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
of monitored modem status conditions. TR, the tone
control register, controls the DTMF generator,
answer and guard tones and RXD output gate used
in the modem initial connect sequence. CR2 is the
primary DSP control interface and CR3 controls
transmit attenuation and receive gain adjustments.
All registers are read/write except for DR and ID,
which are read only. Register control and status bits
are identified below:
REGISTER BIT SUMMARY
ADDRESS
REGISTER
CONTROL
REGISTER
0
CR0
CONTROL
REGISTER
1
CR1
DETECT
REGISTER DR
TONE
CONTROL TR
REGISTER
CONTROL
REGISTER
2
CR2
CONTROL
REGISTER
3
CR3
SPECIAL
REGISTER SR
ID
REGISTER ID
AD-A0
000
001
010
011
100
101
101
110
D7
D6
D5
D4
D3
MODULATION
OPTION
MODULATION
TYPE
1
MODULATION
TYPE
0
TRANSMIT
MODE
2
TRANSMIT
MODE 1
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BYPASS
SCRAMBLER
CLK
CONTROL
RECEIVE
LEVEL
PATTERN
S1 DET
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
RXD
OUTPUT
CONTROL
TRANSMIT
GUARD
TONE
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF 3
SPECIAL
CALL
TRANSMIT
16 WAY
0
REGISTER
INITIALIZE
S1
ACCESS
TXDALT
TRISTATE
RECEIVE
TRANSMIT
TX/RXCLK
OH
GAIN
ATTEN.
BOOST
3
TX BAUD
RX UNSCR.
TXD
0
CLOCK
DATA
0
SOURCE
D2
TRANSMIT
MODE 0
D1
TRANSMIT
ENABLE
RESET
TEST MODE
1
SPECIAL
TONE
DETECT
DTMF2/
4W/FDX
RESET
DSP
CALL
PROGRESS
DETECT
DTMF1/
EXTENDED
OVERSPEED
TRAIN
INHIBIT
TRANSMIT
ATTEN.
2
SQ
SELECT 1
TRANSMIT
ATTEN.
1
SQ
SELECT 0
D0
ANSWER/
ORIGINATE
TEST MODE
0
SIGNAL
QUALITY
DTMF0/
GUARD/
ANSWER
EQUALIZER
ENABLE
TRANSMIT
ATTEN.
0
0
ID
ID
ID
ID
X
X
X
1
NOTE: When a register containing reserved control bit is written into, the reserved bits must be programmed as
0’s.
X = Undefined, mask in software
Page: 9 of 34
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 6.1
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