73K324L データシートの表示（PDF） - Unspecified
部品番号
コンポーネント説明
メーカー
73K324L Datasheet PDF : 30 Pages
| |||
CONTROL REGISTER 0
CR0
000
D7
MODUL.
OPTION
D6
MODUL.
TYPE 1
BIT NO.
D0
NAME
Answer/
Originate
D1
D5, D4,
D3, D2
Transmit
Enable
Transmit
Mode
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
D5
D4
D3
D2
D1
D0
MODUL.
TYPE 0
TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
CONDITION DESCRIPTION
0
Selects Answer mode (transmit in high band, receive in
low band) or in V.23 HDX mode, receive at 1200 bit/s and
transmit at 75 bit/s.
1
Selects Originate mode (transmit in low band, receive in
high band) or in V.23 HDX mode, receive at 75 bit/s and
transmit at 1200 bit/s.
Note: This bit works with Tone Register bits D0 and D6 to
program special tones detected in the Detect Register.
See Detect and Tone Registers.
0
Disables transmit output at TXA.
1
Enables transmit output at TXA.
Note: Transmit Enable must be set to 1 to allow activation
of Answer Tone, DTMF, or Carrier.
D5 D4 D3 D2
0 0 0 0 Selects Power Down mode. All functions are disabled
except the digital interface.
0 0 0 1 Internal Synchronous mode. In this mode TXCLK is an
internally derived 600, 1200 or 2400 Hz signal. Serial
input data appearing at TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.
0 0 1 0 External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally
to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be
supplied externally.
0 0 1 1 Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0 1 0 0 Selects Asynchronous mode - 8 bits/character (1 start bit,
6 data bits, 1 stop bit).
0 1 0 1 Selects Asynchronous mode - 9 bits/character (1 start bit,
7 data bits, 1 stop bit).
0 1 1 0 Selects Asynchronous mode - 10 bits/character (1 start
bit, 8 data bits, 1 stop bit).
0 1 1 1 Selects Asynchronous mode - 11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).
1 X 0 0 Selects FSK operation.
Page: 8 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
Share Link: 