73M1903C-IM/F データシートの表示（PDF） - Teridian Semiconductor Corporation
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73M1903C-IM/F Datasheet PDF : 46 Pages
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73M1903C
Modem Analog Front End
DATA SHEET
SLAVE MODE AND DAISY CHAIN
If the SCLK pin is externally pulled down to ground by a <4.7KΩ resistor, the 79M1903C device is in the
slave mode, after reset. In this mode of operation the serial clock (SCLK) and FS are inputs to 79M1903C
provided by the Master device. The serial clock input must be connected to OSCIN pin while SCLK pin of
73M1903C is unconnected, except for the resistor connected to ground (see Figures 4 and 5). The
73M1903C PLL must be programmed to multiply the serial clock frequency by an appropriate factor in
order to obtain Fsys. Therefore the serial clock has to be continuous and without low frequency jitter (the
high frequency jitter is rejected by the 79M1903C PLL). The SckMode pin is not used since the Master
device provides FS and serial clock.
SDOUT
HOST SDIN
(Slave)
FS
SCLK
MCLK
73M1903C
OSCIN (Master)
SDIN
SDOUT
FS SckMode
SCLK TYPE
"1/0"
"1/0"
SCLK
SDOUT
HOST SDIN
(Master)
FS
73M1903C
OSCIN (Slave)
SDIN
SDOUT
FS SckMode
"x"
SCLK TYPE
"x"
73M1903C Master Mode
"x" : don't care
73M1903C Slave Mode
Figure 4: 73M1903C Host connection in master and slave mode
SDOUT
HOST SDIN
(Slave)
FS
SCLK
MCLK
73M1903C
OSCIN (Master)
S D IN
SDOUT
FS
SckMode
SCLK
TYPE
FSBD
"1/0"
"1/0"
SCLK
SDOUT
HOST SDIN
(Master) FS
73M1903C
OSCIN (Slave)
SDIN
SDOUT
FS SckMode
"x"
SCLK TYPE
"x"
FSBD
73M1903C
OSCIN (Slave)
S D IN
SDOUT
FS
"x"
SckMode
SCLK TYPE
"x"
"x" : don't care
73M1903C
OSCIN (Slave)
SDIN
SDOUT
FS SckMode
"x"
SCLK TYPE
"x"
Daisy chain for Master/Slave mode
Daisy chain for Slave mode
Figure 5: 73M1903C Daisy chaining for master/slave mode and slave modes
In order to daisy chain two or more 73M1903C devices, the master must be programmed into hardware
controlled control frame mode by setting the HC bit (bit 0 in Register01) to “1”, then set FSDEn (bit 3 in
Register06), and then set CkoutEn bit (bit 3 in Register01) to allow the FSD to come through. The first
Page: 9 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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