73S8009C データシートの表示（PDF） - Teridian Semiconductor Corporation

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73S8009C

Versatile Power Management and Smart Card Interface IC

Teridian Semiconductor Corporation 

73S8009C Data Sheet

DS_8009C_025

Pin

Name

Pin

Pin

(QFN32) (QFN20)

Type

Equivalent

Circuit

Description

VPC

26

16

PSI Figure 14 Power supply source for main voltage

converter circuit. A 10 µF and a 0.1 µF

ceramic capacitor must be connected to this

pin.

VBAT

25

N/A

Alternate power source input, typically from

two series cells, V > 4 V.

VBUS

23

N/A

Alternate power source input from USB

connector or hub.

LIN

27

17

PSI Figure 14 Connection to 10 µH inductor for internal step

up converter. Note: inductor must be rated for

400 mA maximum peak current.

VP

15

9

PSO Figure 14 Intermediate output of main converter circuit.

Requires an external 4.7 µF low ESR filter

capacitor to GND

GND

28,31

18

–

Ground.

Microcontroller Interface

CS

OFF

12

N/A

I

Figure 19 When CS = 1, the control and signal pins are

configured normally. When CS is set low,

CMDVCC%, RSTIN, and CMDVCC#. are

latched. I/OUC, AUX1UC, and AUX2UC are

set to high-impedance pull-up mode and do not

pass data to or from the smart card. Signals

RDY and OFF are disabled to prevent a low

output and the internal pull-up resistors are

disconnected.

32

1

O Figure 13 Interrupt signal to the processor. Active Low -

Multi-function indicating fault conditions and

card presence. Open drain output configuration

– It includes an internal 20 kΩ pull-up to VDD.

Pull-up is disabled in Power down state and CS

= 0 modes.

I/OUC

AUX1UC

AUX2UC

1

2

IO Figure 18 System controller data I/O to/from the card.

Includes a pull-up resistor to VDD.

2

N/A

IO Figure 18 System controller auxiliary data I/O to/from the

card. Includes a pull-up resistor to VDD.

3

N/A

IO Figure 18 System controller auxiliary data I/O to/from the

card. Includes a pull-up resistor to VDD.

8

Rev. 1.4

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