ICS8431CM-01 データシートの表示（PDF） - Integrated Circuit Systems

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ICS8431CM-01

200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS8431-01

200MHZ, LOW JITTER,

LVPECL FREQUENCY SYNTHESIZER

TABLE 1. PIN DESCRIPTIONS

Number

1-9, 19,

23, 24, 28

10, 11

12

Name

nc

SSC_CTL0,

SSC_CTL1

GND

13

TEST_ I/O

14, 27

15

VDD

GND

16, 17 nFOUT, FOUT

18

20

21

22

25, 26

27

VDDO

RESERVED

VEE

VDDA

XTAL1, XTAL2

VDDI

Type

Unused

Input

Power

Input /

Output

Power

Power

Pullup

Output

Power

Reserve

Power

Power

Input

Power

Description

Unused pins.

SSC control pins. LVTTL/LVCMOS interface levels.

Ground pin for core and test output.

Programmed as defined in Table 3 Function Table..

Power supply pin for core and test output.

Ground pin for output.

These differential outputs are main output drivers for the synthesizer.

They are compatible with terminated positive referenced LVPECL

logic.

Power supply pin for output.

Reserve pin.

Ground pin.

PLL power supply pin.

Crystal oscillator input.

Input and core power supply pin. Connect to 3.3V.

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

RPULLUP

RPULLDOWN

Parameter

Input Pin Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

51

51

Maximum

4

Units

pF

KΩ

KΩ

TABLE 3. SSC CONTROL INPUTS FUNCTION TABLE

Inputs

SSC_CTL1 SSC_CTL0

0

0

0

1

TEST_I/O

Source

Internal

PLL

SSC

Disabled

Enabled

Outputs

FOUT,

nFOUT

TEST_I/O

fXTAL ÷ 32

fXTAL ÷ 16

÷M

200MHz

Hi-Z

1

0

External Disabled Test Clk

Input

1

1

PLL Disabled 200MHz

Hi-Z

NOTE 1: Used for in house debug and characterization.

Operational Modes

PLL bypass; Oscillator, oscillator, M and N

dividers test mode. NOTE 1

Default SSC; Modulation Factor = ½ Percent

Diagnostic Mode; NOTE 1

(1MHz ≤ Test Clk ≤ 200MHz)

No SSC Modulation

ICS8431CM-01

www.icst.com/products/hiperclocks.html

2

REV. A JUNE 5, 2001

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