74ACTQ16646 データシートの表示（PDF） - Fairchild Semiconductor
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74ACTQ16646 Datasheet PDF : 9 Pages
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Extended AC Electrical Characteristics
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = Com
VCC = Com
CL = 50 pF
CL = 250 pF
Symbol
Parameter
16 Outputs Switching
Units
(Note 12)
(Note 13)
Min
Typ
Max
Min
Max
tPHL
Propagation Delay
4.1
tPLH
Clock to Bus
4.2
tPHL
Propagation Delay
4.0
tPLH
Bus to Bus
4.7
tPHL
Propagation Delay
3.8
tPLH
Select to Bus
4.3
(w/An or Bn HIGH or LOW)
10.1
6.1
14.5
ns
10.1
6.0
14.8
10.0
5.4
13.7
ns
10.7
5.9
13.5
9.6
5.7
14.2
ns
10.9
6.1
15.5
tPZL
tPZH
tPLZ
tPHZ
tPZL
tPZH
tPLZ
tPHZ
tOSHL
(Note 11)
Enable Time
G to An/Bn
Disable Time
G to An/Bn
Enable Time
DIR to An/Bn
Disable Time
DIR to An/Bn
Pin-to-Pin Skew
Clock to Bus
5.0
12.7
(Note 14)
ns
4.1
11.3
3.2
8.3
(Note 15)
ns
3.5
8.6
4.1
11.3
(Note 14)
ns
4.4
13.0
2.9
9.5
(Note 15)
ns
3.4
9.7
1.0
ns
tOSLH
(Note 11)
Pin-to-Pin Skew
Clock to Bus
1.0
ns
tOSHL
(Note 11)
Pin-to-Pin Skew
Bus to Bus
1.0
ns
tOSLH
(Note 11)
Pin-to-Pin Skew
Bus to Bus
1.0
ns
tOSHL
(Note 11)
Pin-to-Pin Skew
Select to Bus
1.0
ns
(w/An or Bn HIGH or LOW)
tOSLH
(Note 11)
Pin-to-Pin Skew
Select to Bus
1.2
ns
(w/An or Bn HIGH or LOW)
tOST
(Note 11)
Pin-to-Pin Skew
Clock to Bus
2.1
ns
tOST
(Note 11)
Pin-to-Pin Skew
Bus to Bus
1.0
ns
tOST
(Note 11)
Pin-to-Pin Skew
Select to Bus
2.7
ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW to HIGH and/or HIGH to
LOW (tOST).
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 14: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 15: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
Units
Conditions
4.5
pF
VCC = 5.0V
95
pF
VCC = 5.0V
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