Philips Semiconductors
Bus buffer/line driver; 3-state
Product specification
74AHC1G126; 74AHCT1G126
handbook, full pagewidth
VI
OE input
GND
VCC
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
tPLZ
tPZL
tPHZ
VOL +0.3 V
VOH −0.3 V
VM
tPZH
VM
output
enabled
output
disabled
output
enabled
MNA129
FAMILY
AHC1G
AHCT1G
VI INPUT
VM
VM
REQUIREMENTS INPUT OUTPUT
GND to VCC
GND to 3.0 V
50% VCC 50% VCC
1.5 V
50% VCC
Fig.6 The 3-state enable and disable times.
handbook, full pagewidth
VI
PULSE
GENERATOR
VCC
VO
D.U.T.
RT
S1
RL =
1000 Ω
VCC
open
GND
CL
MNA232
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
open
VCC
GND
2002 Jun 06
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”).
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.7 Load circuitry for switching times.
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