N74ALS161BN データシートの表示（PDF） - Philips Electronics
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N74ALS161BN Datasheet PDF : 14 Pages
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Philips Semiconductors
4-bit binary counter
Product specification
74ALS161B/74ALS163B
74ALS161B 4-bit binary counter, asynchronous reset
74ALS163B 4-bit binary counter, synchronous reset
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive edge-triggered clock
• Asynchronous reset (74ALS161B)
• Synchronous reset (74ALS163B)
• High speed synchronous expansion
• Typical count rate of 140MHz
TYPE
74ALS161B
74ALS163B
TYPICAL fMAX
140MHz
140MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
10mA
10mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP 74ALS161BN, 74ALS163BN
16-pin plastic SO 74ALS161BD, 74ALS163BD
16-pin plastic SSOP
Type II
74ALS161BDB,
74ALS163BDB
DRAWING
NUMBER
SOT38-4
SOT109-1
SOT338-1
DESCRIPTION
Synchronous presettable 4-bit binary counters (74ALS161B,
74ALS163B) feature an internal carry look-ahead and can be used
for high speed counting. Synchronous operation is provided by
having all flip-flops clocked simultaneously on the positive-going
edge of the clock. The clock input is buffered.
The outputs of the counters may be preset to High or Low level. A
Low level at the parallel enable (PE) input disables the counting
action and causes the data at the D0 – D3 inputs to be loaded into
the counter on the positive-going edge of the clock (provided that
the setup and hold requirements for PE are met). Preset takes place
regardless of the levels at count enable (CEP, CET) inputs.
A Low level at the master reset (MR) input sets all the four outputs
of the flip-flops (Q0 – Q3) in 74ALS161B to Low levels, regardless of
the levels at CP, PE, CET and CEP inputs (thus providing an
asynchronous clear function).
For the 74ALS163B the clear function is synchronous. A Low level
at the synchronous reset (SR) input sets all four outputs of the
flip-flops (Q0 – Q3) to Low levels after the next positive-going
transition on the clock (CP) input ( provided that the setup and hold
time requirements for SR are met). This action occurs regardless of
the levels at CP, PE, CET and CEP inputs. The synchronous reset
feature enables the designer to modify the maximum count with only
one external NAND gate (see Figure 1).
The carry look-ahead simplifies serial cascading of the counters.
Both count enable (CEP and CET) inputs must be High to count.
The CET input is fed forward to enable the TC output. The TC
output thus enabled will produce a High output pulse of a duration
approximately equal to the High level output of Q0. This pulse can
be used to enable the next cascaded stage (see Figure 2).
The TC output is subjected to decoding spikes due to internal race
conditions, Therefore, it is not recommended for use as clock or
asynchronous reset for flip-flops, registers, or counters.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
CEP
Count enable parallel input (active-Low)
1.0/1.0
CET
Count enable trickle input (active-Low)
1.0/1.0
CP
Clock input (active rising edge)
1.0/1.0
PE
Parallel enable input (active-Low)
1.0/1.0
MR
Asynchronous master reset input (active-Low) for 74ALS161B
1.0/1.0
SR
Asynchronous reset input (active-Low) for 74ALS163B
1.0/1.0
Q0 – Q3
Flip-flop outputs
20/80
TC
Terminal count output (active-Low)
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
20/80
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
0.4mA/8mA
1991 Feb 08
2
853–1350 01670
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