74F175AN データシートの表示（PDF） - Philips Electronics
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74F175AN Datasheet PDF : 10 Pages
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Philips Semiconductors
Quad D flip-flop
Product specification
74F175A
FEATURES
• Four edge-triggered D-type flip-flops
• Buffered common clock
• Buffered asynchronous Master Reset
• True and complementary outputs
• Industrial temperature range available (–40°C to +85°C)
• PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with
individual D inputs and both Q and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independently of clock or data
inputs by a Low voltage level on the MR input. The device is useful
for applications where both true and complementary outputs are
required, and the CP and MR are common to all storage elements.
PIN CONFIGURATION
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
SF00718
TYPE
74F175A
TYPICAL fmax
160MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
22mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F175AN
N74F175AD
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
I74F175AN
I74F175AD
PKG. DWG. #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
D0 – D3 Data inputs
MR
Master reset input (active–Low)
CP
Clock input (active rising edge)
Q0–Q3 True outputs
Q0–Q3 Complementary outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F175A
74F175A
74F175A
74F (U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
2000 Jun 30
2
853–0047 24024
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