74F539 データシートの表示（PDF） - Fairchild Semiconductor
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74F539 Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
A0a–A1a
A0b–A1b
Ea, Eb
OEa, OEb
Pa, Pb
O0a–O3a
O0b–O3b
Side A Address Inputs
Side B Address Inputs
Enable Inputs (Active LOW)
Output Enable Inputs (Active LOW)
Polarity Control Inputs
Side A 3-STATE Outputs
Side B 3-STATE Outputs
Truth Table
(each half)
Function
OE
High Impedance
H
Disable
L
Active HIGH
L
Output
L
(P = L)
L
L
Active LOW
L
Output
L
(P = H)
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Logic Diagram (one half shown)
Inputs
E
A1
X
X
H
X
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
H
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
150/40 (33.3)
A0
O0
X
Z
X
L
H
H
L
L
L
H
L
L
L
H
H
L
H
H
H
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
−3 mA/24 mA (20 mA)
Outputs
O1
O2
O3
Z
Z
Z
On = P
L
L
L
H
L
L
L
H
L
L
L
H
H
H
H
L
H
H
H
L
H
H
H
L
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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