74HC175D データシートの表示（PDF） - Philips Electronics

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74HC175D

Quad D-type flip-flop with reset; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Quad D-type flip-flop with reset; positive-edge trigger

AC WAVEFORMS

Product specification

74HC/HCT175

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.6

Waveforms showing the clock (CP) to

outputs (Qn, Qn) propagation delays, the

clock pulse width, output transition times

and the maximum clock pulse frequency.

The shaded areas indicate when the input is

permitted to change for predictable output

performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.7 Waveforms showing the data set-up and

hold times for the data input (Dn).

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.8

Waveforms showing the master reset (MR)

pulse width, the master reset to outputs

(Qn, Qn) propagation delays and the master

reset to clock (CP) removal time.

1998 Jul 08

7

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