74HC297 データシートの表示（PDF） - Philips Electronics

部品番号

コンポーネント説明

メーカー

74HC297

Digital phase-locked-loop filter

Philips Electronics 

Philips Semiconductors

Digital phase-locked-loop filter

Product specification

74HC/HCT297

The carry and borrow pulses go to the

increment/decrement (I/D) circuit which, in the absence of

any carry or borrow pulses has an output that is 1/2 of the

input clock (I/DCP). The input clock is just a multiple, 2N, of

the loop centre frequency. In response to a carry or borrow

pulse, the I/D circuit will either add or delete a pulse at

I/DOUT. Thus the output of the I/D circuit will be

Nfc + (kd∅eMfc)/2K.

The output of the N-counter (or the output of the

phase-locked-loop) is thus: fo = fc + (kdφeMfc)/2KN.

If this result is compared to the equation for a first-order

analog phase-locked-loop, the digital equivalent of the

gain of the VCO is just Mfc/2KN or fc/K for M = 2N.

Thus the simple first-order phase-locked-loop with an

adjustable K-counter is the equivalent of an analog

phase-locked-loop with a programmable VCO gain.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL PARAMETER

CONDITIONS

tPHL/ tPLH

fmax

CI

CPD

propagation delay

I/DCP to I/DOUT

φA1, φB to XORPDOUT

φB, φA2 to ECPDOUT

maximum clock frequency

KCP

I/DCP

input capacitance

power dissipation capacitance per package

CL = 15 pF; VCC = 5 V

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

TYPICAL

HC

HCT

15

18

13

13

19

19

63

68

41

40

3.5

3.5

18

19

UNIT

ns

ns

ns

MHz

MHz

pF

pF

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

3

Share Link: