DM74LS10N データシートの表示（PDF） - Fairchild Semiconductor
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DM74LS10N Datasheet PDF : 4 Pages
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August 1986
Revised March 2000
DM74LS10
Triple 3-Input NAND Gate
General Description
This device contains three independent gates each of
which performs the logic NAND function.
Ordering Code:
Order Number Package Number
Package Description
DM74LS10M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS10N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y = ABC
Inputs
A
B
C
X
X
L
X
L
X
L
X
X
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Output
Y
H
H
H
L
© 2000 Fairchild Semiconductor Corporation DS006349
www.fairchildsemi.com
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