DM74LS194 データシートの表示（PDF） - Fairchild Semiconductor
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DM74LS194 Datasheet PDF : 6 Pages
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Function Table
Inputs
Outputs
Mode
Serial
Parallel
Clear
Clock
S1 S0
Left
Right A B C D QA
QB
QC
QD
L
XX
X
X
X
XXXX L
L
L
L
H
XX
L
X
X
X X X X QA0 QB0 QC0 QD0
H
HH
↑
X
X
abcd a
b
c
d
H
LH
↑
X
H
X X X X H QAn QBn QCn
H
LH
↑
X
L
X X X X L QAn QBn QCn
H
HL
↑
H
X
X X X X QBn QCn QDn H
H
HL
↑
L
X
X X X X QBn QCn QDn L
H
LL
X
X
X
X X X X QA0 QB0 QC0 QD0
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a, b, c, d = The level of steady state input at inputs A, B, C or D, respectively.
QA0, QB0, QC0, QD0 = The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established.
QAn, QBn, QCn, QDn = The level of QA, QB, QC, respectively, before the most-recent ↑ transition of the clock.
Logic Diagram
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