74LVC02AD データシートの表示（PDF） - Philips Electronics
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74LVC02AD Datasheet PDF : 10 Pages
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Philips Semiconductors
Quad 2-input NOR gate
Product specification
74LVC02A
FEATURES
• Wide supply range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5V
• CMOS low power consumption
• Direct interface with TTL levels
• 5-volt tolerant inputs, for interfacing with 5-volt logic
DESCRIPTION
The 74LVC02A is a high performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC02A provides the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL
Propagation delay
tPLH
nA, nB to nY
CL = 50 pF;
VCC = 3.3 V
CI
Input capacitance
CPD
Power dissipation capacitance per gate Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi )ȍ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
ȍ (CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
2.8
5.0
28
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC02A D
74LVC02A DB
74LVC02A PW
NORTH AMERICA
74LVC02A D
74LVC02A DB
74LVC02APW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
14 VCC
13 4Y
12 4B
11 4A
10 3Y
9 3B
8 3A
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1, 4, 10, 13 1Y – 4Y
2, 5, 8, 11 1A – 4A
3, 6, 9, 12 1B – 4B
7
GND
14
VCC
NAME AND FUNCTION
Data outputs
Data inputs
Ground (0 V)
Positive supply voltage
SV00389
1998 Apr 28
2
853-2019 19310
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