74LVC1G175 データシートの表示（PDF） - NXP Semiconductors.
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74LVC1G175 Datasheet PDF : 17 Pages
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NXP Semiconductors
12. Waveforms
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
VI
D input
GND
VI
CP input
GND
VOH
Q output
VOL
VM
th
tsu
th
tsu
1/fmax
VM
tW
tPHL
VM
tPLH
001aaa465
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 7. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to
D hold times, and the maximum clock pulse frequency
VI
MR input
GND
VI
CP input
GND
VOH
Q output
VOL
VM
tW
t rec
t PHL
VM
VM
001aaa464
Measurement points are given in Table 9.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig 8. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width, and the MR to
CP recovery time
74LVC1G175_3
Product data sheet
Rev. 03 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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