74LVX373(2004) データシートの表示（PDF） - STMicroelectronics

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74LVX373
(Rev.:2004)

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX373

Figure 2: Input Equivalent Circuit

Table 2: Pin Description

PIN N°

1

3, 4, 7, 8, 13,

14, 17, 18

2, 5, 6, 9, 12,

15, 16,19

11

10

20

SYMBOL

OE

D0 to D7

NAME AND FUNCTION

3 State Output Enable

Input (Active LOW)

Data Inputs

Q0 to Q7 3-State Outputs

LE

GND

VCC

Latch Enable Input

Ground (0V)

Positive Supply Voltage

Table 3: Truth Table

INPUTS

OE

LE

D

H

X

X

L

L

X

L

H

L

L

H

H

X : Don’t Care

Z : High Impedance

* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level

Figure 3: Logic Diagram

OUTPUT

Q

Z

NO CHANGE*

L

H

This logic diagram has not be used to estimate propagation delays

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