GM72V66841CLT-8 データシートの表示（PDF） - LG

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GM72V66841CLT-8

2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM

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Pin Description(Continued)

GM72V66841CT/CLT

Pin Name

DQ0 ~ DQ7

(I/O pins)

VCC and VCCQ

(Power supply pins)

DESCRIPTION

Data is input and output from these pins. These pins are the same as those of a

conventional DRAM.

3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output

buffer.)

VSS and VSSQ

Ground is connected. (VSS is for the internal circuit and VSSQ is for the output

(Power supply pins) buffer.)

NC

No Connection pins.

Command Operation

Command Truth Table

The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE

and address pins.

Function

Symbol

CKE

n-1 n

CS

RAS CAS

WE

A12~

A13

A10

A0~

A11

Ignore command

DESL H X H X X X X X X

No Operation

NOP H X L H H H X X X

Burst stop in full page

BST

HX L H H L X X X

Column address and

read command

READ H X L H L H V L V

Read with auto-Precharge READ A H X L H L H V H V

Column address and

write command

WRIT H X L H L L V L V

Write with auto-Precharge WRIT A H X L H L L V H V

Row address strobe and

bank active

ACTV H X L

L

HHVVV

Precharge select bank

PRE

HX L L H L V L X

Precharge all banks

PALL H X L L H L X H X

Refresh

REF/SELF H V L L L H X X X

Mode register set

MRS H X L L L L V V V

* Notes : H: VIH, L: VIL, X: VIH or VIL, V: Valid address input

4

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