74VHC139 データシートの表示（PDF） - STMicroelectronics

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74VHC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

STMicroelectronics 

74VHC139

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

s HIGH SPEED: tPD = 5.0 ns (TYP.) at VCC = 5V

s LOW POWER DISSIPATION:

ICC = 4 µA (MAX.) at TA=25°C

s HIGH NOISE IMMUNITY:

VNIH = VNIL = 28% VCC (MIN.)

s POWER DOWN PROTECTION ON INPUTS

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 8 mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 139

s IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74VHC139 is an advanced high-speed

CMOS DUAL 2 TO 4 LINE DECODER/

DEMULTIPLEXER fabricated with sub-micron

silicon gate and double-layer metal wiring C2MOS

technology.

The active low enable input can be used for gating

or as a data input for demultiplexing applications.

While the enable input is held high, all four outputs

are high independently of the other inputs.

SOP

TSSOP

ORDER CODES

PACKAGE

SOP

TSSOP

TUBE

74VHC139M

T&R

74VHC139MTR

74VHC139TTR

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2001

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