75N43102 データシートの表示（PDF） - Integrated Device Technology
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75N43102 Datasheet PDF : 3 Pages
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NETWORK SEARCH ENGINE
32K x 72 Entries
Datasheet
Brief
75N43102
To request the full IDT75N43102 datasheet, please contact your local
IDT Sales Representative or call 1-800-345-7015
Device Description
IDT provides proven, industry-leading network search engines
(NSEs) that enable and accelerate the intelligent processing of network
services in communications equipment. As a part of the complete IDT
classification subsystem that includes content inspection engines, the IDT
family of NSEs delivers high-performance, feature-rich, easy-to-use,
integrated search accelerators.
The IDT 75N43102 is ideally suited for cost-sensitive applications
in the enterprise and access markets. It is a full-ternary 32K x 72 entry
device where each entry location in the NSE has both a Data entry and
an associated Mask entry. The NSE devices integrate content addres-
sable memory (CAM) technology with high-performance logic. The
device can perform Lookup operations plus Read and Write maintenance
operations.
The IDT 75N43102 NSE device has a bi-directional bus that is a
multiplexed address and data bus that can support 62.5 million sustained
searches per second. This device can be configured to enable multiple
width lookups from 72 to 288 bits wide. The IDT 75N43102 requires a
1.5-volt VDD1 supply and a 2.5-volt VDD2 supply.
The IDT 75N43102 NSE utilizes the latest high-performance 1.5V
CMOS processing technology and is packaged in a JEDEC Standard,
256 pin low profile Ball Grid Array.
Block Diagram
C ONFI GIN
MA TCHI N
CLK2X
PHASEN
÷÷ 2
CCLK
RST
REQSTB
Command Bus
INSTRUCTION
R/W
Request REQDATA
Bus
D
E
C
Ad dres s
O
D
E
DATA
Configuration Registers
CO NFI GOU T
P
R
S
I
I
O
Z
R
E
I
Index
32K X 72
T
Bus
L
Y
O
G
E
I
N
C
C
O
D
E
R
Global Mask Registers
MATCHOUT
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System Configurations
The IDT NSEs are designed to fulfill the needs of various types of
networking systems. In solutions requiring data searching such as
routers, a system configuration as shown in Figure 1.0 may be realized.
In this compatible configuration, the NSE interfaces directly to an
ASIC/ FPGA for lookups and routes an Index directly back to the ASIC/
FPGA. Control of the associated handshake signals is provided by the
NSEs for this configuration.
Figure 1.0 ASIC / FPGA Compatible NSE
ASIC
or
FPGA
IDT 75N43102
Network
Search
Engine
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1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
APRIL 2004
DSC-6435/0B
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