78P2342-IGT データシートの表示（PDF） - Teridian Semiconductor Corporation

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78P2342-IGT

2-port E3/DS3/STS-1 LIU with Jitter Attenuator

Teridian Semiconductor Corporation 

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION

DETECT

The 78P2342JAT includes a selectable B3ZS/HDB3

Encoder/Decoder (ENDEC). The ENDEC function

can be enabled or disabled through pin selection or

register setting as shown below.

ENDECB

bit/pin

RPOSx

RNEGx

0/L

NRZ data

Receive Line Code

Violation Indicator

1/H

Positive AMI

Negative AMI

When the ENDEC is enabled, the decoder

generates a composite NRZ logic data stream

following the B3ZS (for DS3/STS-1) or HDB3 (for E3)

substitution codes via the RPOSx pins:

The decoder also detects Receive Line Code

Violations (RLCV) and outputs a pulse via the

RNEG pin. Three different classes of line code

violations are detected.

1) Too many zeros: More than two (three)

consecutive zeros in B3ZS (HDB3) mode.

2) Not enough zeros between bipolar pulse (B)

and bipolar violation pulse (V): (B,V) for B3ZS.

(B,V) or (B,0,V) for HDB3.

3) Code violation: Even number of bipolar pulses

(B) detected between bipolar violation pulses

(V).

When the ENDEC is disabled, the 78P2342JAT

outputs a dual rail data stream via the RPOSx and

RNEGx pins. In this mode, the Framer/Mapper

providing the ENDEC function typically detects Line

Code Violations.

On the transmit side, when the ENDEC is enabled,

NRZ input data is encoded to Positive and Negative

AMI logic data following the B3ZS (for DS3/STS-1)

or HDB3 (for E3) substitution codes. The NRZ data

is input to the TPOS pin as shown below:

ENDECB

bit/pin

TPOSx

TNEGx

0/L

NRZ data

‘Don’t Care’

1/H

Positive AMI

Negative AMI

TRANSMITTER OPERATION

Both transmitters are enabled by their corresponding

TXEN bit. When enabled, each transmitter accepts

logic level clock and data signals and generates

current pulses on the LOUTPx and LOUTNx pins.

When properly connected to a 1:2CT center-tapped

transformer, a standards compliant AMI pulse is

generated which can drive a 75Ω coaxial cable.

When the recommended transformer is used and

when DS3 mode is selected, the transmitted pulse

shape at the end of the 75Ω terminated cable of 0 to

450 feet will fit the DS3 template in ANSI T1.102-

1993 and Telcordia GR-499-CORE. For STS-1

applications, the transmitted pulse for a short cable

meets the requirements of Telcordia GR-253-CORE.

For E3 applications, the transmitted pulse for a short

cable meets the requirements of ITU-T G.703.

In either DS3 and STS-1 modes, the LBOx pin or

LBO bit should be set high for short cable (< 225 ft),

and should be set low for long cable (> 225 ft). The

LBO settings are ignored in E3 mode.

RCLK/TCLK POLARITY REVERSAL

To simplify the interface with various framer circuitry,

TCLK polarity can be internally inverted by setting

the TCLKP bit, and RCLK polarity can be inverted

by setting the RCLKP bit. Both bits are located in

the Master Control Register (MSCR).

REMOTE (DIGITAL) LOOPBACK

When the Register Control bit, REGEN, is disabled

and the LPBKx pin is floating; or when the Register

Control bit, REGEN, is enabled and the RLBK bit is

set, RCLKx, RNEGx, and RPOSx outputs are

internally looped back to the TCLKx, TNEGx, and

TPOSx inputs respectively.

Page 4 of 36

2005 Teridian Semiconductor Corporation

Rev 2.2

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