78P2342JAT-IGT データシートの表示（PDF） - Teridian Semiconductor Corporation
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78P2342JAT-IGT Datasheet PDF : 36 Pages
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REGISTER DESCRIPTION
REGISTER ADDRESSING
Address Bits
Assignment
Bit 7
PA[3]
Bit 6
Bit 5
Port Address
PA[2]
PA[1]
Bit 4
PA[0]
78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
Bit 3
Bit 2
Bit 1
Sub-Address
SA[2]
SA[1]
SA[0]
Bit 0
Read/
Write
R/W*
REGISTER TABLE
a) PA[3:0] = 0 : Global Registers
Sub
Addr
0
1
2
3
4
5
6
7
Reg.
Name
MSCR
(R/W)
INTC
(R/W)
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Description
Master Control
Interrupt Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
REGEN
<0>
INPOL
<0>
--
<0>
--
--
<0>
<0>
Bit 6
DS3
<X>
--
--
<0>
--
--
<0>
<0>
Bit 5
E3
<X>
--
--
<0>
--
--
<0>
<0>
Bit 4
Bit 3
ENDECB RCLKP
<0>
<0>
--
--
--
--
<0>
<0>
--
--
--
--
<0>
<0>
<0>
<0>
Bit 2
TCLKP
<0>
JAER
<0>
--
<0>
--
--
<0>
<0>
Bit 1
--
RXER
<1>
--
<0>
--
--
<0>
<0>
Bit 0
SRST
<0>
TXER
<1>
--
<0>
--
--
<0>
<0>
b) PA[3:0] = 1-2 : Port-Specific Registers
Sub
Addr
0
1
2
3
4
Reg.
Name
MDCR
(R/W)
STAT
(R/O)
RSVD
JACR
(R/W)
RSVD
Description
Mode Control
Status Monitor
Reserved
Jitter Attenuator
Control
Reserved
Bit 7
PDTX
<0>
FERR
<1>
JAEN
<X>
--
5 RSVD
Reserved
<0>
6 RSVD
Reserved
--
7 RSVD
Reserved
<0>
Bit 6
PDRX
<0>
--
<1>
JASL
<X>
--
--
--
<0>
Bit 5
LBO
<1>
--
<0>
JLBK
<0>
--
Bit 4
LLBKA
<0>
--
<1>
<0>
--
Bit 3
LLBKB
<0>
LOS
<0>
ESP[1]
<1>
--
Bit 2
RLBK
<0>
TXNW
<1>
ESP[0]
<1>
--
--
<0>
<0>
<0>
--
--
--
--
<0>
<0>
<0>
<0>
Bit 1
MON
<0>
--
<0>
<0>
--
<0>
--
<0>
Bit 0
TXEN
<1>
SGLO
<0>
JABW
<X>
--
<0>
--
<0>
Note: Shaded registers in Register Table are reserved for Teridian internal use only. Accessing reserved or
undefined registers may cause undesirable operation.
Page 7 of 36
2005 Teridian Semiconductor Corporation
Rev 2.2
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