78P2342-IGT データシートの表示（PDF） - Teridian Semiconductor Corporation

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78P2342-IGT

2-port E3/DS3/STS-1 LIU with Jitter Attenuator

Teridian Semiconductor Corporation 

REGISTER DESCRIPTION (continued)

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

ADDRESS 0-1: INTERRUPT CONTROL REGISTER

This register selects the events that would cause the respective interrupt pin (INTRx) for each of the ports to be

activated. User may set as many bits as required.

BIT

NAME

TYPE

DFLT

VALUE

DESCRIPTION

Interrupt Pin Polarity Selection:

7 INPOL R/W

0 0 : Interrupt output is active-low

1 : Interrupt output is active-high

6:3 RSVD R/O

-- Reserved

2 JAER R/W

1 RXER R/W

0 TXER R/W

Jitter Attenuator Error Event:

0

When set, JAT FIFO overflow or underflow (as indicated by the FERR bit)

will cause an interrupt to be flagged.

Receiver Error Event:

1

When set, loss of receive signal (as indicated by the LOS bit) will cause

an interrupt to be flagged.

Transmitter Error Event:

1

When set, transmitter fault (as indicated by the TXNW bit) will cause an

interrupt to be flagged.

Page 9 of 36

2005 Teridian Semiconductor Corporation

Rev 2.2

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