78Q2120C09-64CGT データシートの表示（PDF） - Teridian Semiconductor Corporation

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78Q2120C09-64CGT

10/100BASE-TX Transceiver

Teridian Semiconductor Corporation 

78Q2120C

10/100BASE-TX

Transceiver

REGISTER DESCRIPTION

The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported

registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the

MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those

which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’. The registers specific

to the 78Q2120C occupy address space MR16-22.

ADDRESS

0

1

2

3

4

5

6

7

8-14

15

16

17

18

19

20-22

SYMBOL

MR0

MR1

MR2

MR3

MR4

MR5

MR6

MR7

MR8-14

MR15

MR16

MR17

MR18

MR19

MR20-MR22

NAME

Control

Status

PHY Identifier 1

PHY Identifier 2

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Not Implemented

Reserved

Not Implemented

Vendor Specific

Interrupt Control/Status Register

Diagnostic Register

Transceiver Control

Reserved

DEFAULT (HEX)

(3100)

(7809)

000E

70C9

(01E1)

0000

0000

0000

0000

0000

(0140)

0000

0000

4XXX

0000

Legend:

TYPE

R

SC

0/1

DESCRIPTION

Readable by management.

Writeable by management. Self

Clearing.

Default value upon power up or

reset.

TYPE

W

RC

(0/1)

DESCRIPTION

Writeable by management.

Readable by management.

Cleared upon a read operation.

Default value dependent on pin

settings. The value in bracket

indicates typical case.

Page: 10 of 35

© 2009 Teridian Semiconductor Corporation

Rev 1.3

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