82574L データシートの表示（PDF） - Intel

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82574L

82574 GbE Controller

Intel 

Datasheet—82574 GbE Controller

Contents

1.0 Introduction ............................................................................................................ 10

1.1 Scope .............................................................................................................. 10

1.2 Number Conventions ......................................................................................... 10

1.3 Acronyms......................................................................................................... 11

1.4 Reference Documents ........................................................................................ 12

1.5 82574 Architecture Block Diagram ....................................................................... 13

1.6 System Interface............................................................................................... 13

1.7 Features Summary ............................................................................................ 13

1.8 Product Codes................................................................................................... 16

2.0 Pin Interface ........................................................................................................... 18

2.1 Pin Assignments................................................................................................ 18

2.2 Pull-Up/Pull-Down Resistors and Strapping Options ................................................ 19

2.3 Signal Type Definition ........................................................................................ 19

2.3.1 PCIe ..................................................................................................... 19

2.3.2 NVM Port............................................................................................... 20

2.3.3 System Management Bus (SMBus) Interface .............................................. 21

2.3.4 NC-SI and Testability .............................................................................. 21

2.3.5 LEDs .................................................................................................... 22

2.3.6 PHY Pins ............................................................................................... 22

2.3.7 Miscellaneous Pin ................................................................................... 23

2.3.8 Power Supplies and Support Pins .............................................................. 24

2.4 Package ........................................................................................................... 25

3.0 Interconnects .......................................................................................................... 26

3.1 PCIe ................................................................................................................ 26

3.1.1 Architecture, Transaction, and Link Layer Properties ................................... 27

3.1.2 General Functionality .............................................................................. 28

3.1.3 Transaction Layer................................................................................... 28

3.1.4 Flow Control .......................................................................................... 33

3.1.5 Host I/F ................................................................................................ 35

3.1.6 Error Events and Error Reporting .............................................................. 36

3.1.7 Link Layer ............................................................................................. 39

3.1.8 PHY ...................................................................................................... 40

3.1.9 Performance Monitoring .......................................................................... 41

3.2 Ethernet Interface ............................................................................................. 41

3.2.1 MAC/PHY GMII/MII Interface ................................................................... 41

3.2.2 Duplex Operation for Copper PHY/GMII/MII Operation ................................. 42

3.2.3 Auto-Negotiation & Link Setup Features .................................................... 43

3.2.4 Loss of Signal/Link Status Indication ......................................................... 46

3.2.5 10/100 Mb/s Specific Performance Enhancements....................................... 47

3.2.6 Flow Control .......................................................................................... 48

3.3 SPI Non-Volatile Memory Interface ...................................................................... 51

3.3.1 General Overview................................................................................... 51

3.3.2 Supported NVM Devices .......................................................................... 51

3.3.3 NVM Device Detection ............................................................................. 52

3.3.4 Device Operation with an External EEPROM................................................ 53

3.3.5 Device Operation with Flash..................................................................... 53

3.3.6 Shadow RAM ......................................................................................... 53

3.3.7 NVM Clients and Interfaces ...................................................................... 55

3.3.8 NVM Write and Erase Sequence................................................................ 56

3.4 System Management Bus (SMBus) ...................................................................... 58

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